1. Field of the Invention
The present invention relates to a method of making a semiconductor device using a circuit-component isolation process.
2. Description of the Related Art
With the advent of a sub-micron technology, the circuit-component isolation method is changing from the local oxidation of silicon (LOCOS) to the shallow trench isolation (STI) method. The STI method is a technique comprising the steps of forming a trench in a substrate and burying an insulation film in the trench to form a circuit-component isolation region.
FIGS. 7(a)-(d) show an example of the STI process.
First of all, an oxide film 2 is formed on a surface of silicon substrate 1 by a thermal oxidation process to a thickness of 150 Angstroms, and a Si3N4 film 3 is deposited by a chemical vapor deposition (CVD) process to a thickness of 2000 Angstroms. Then, patterning is made by the conventional photolithography and dry-etching so as to keep the Si3N4 layer 3 and the pad oxide film 2 only in predetermined active regions. Then, the silicon substrate 1 is etched about 4000 Angstroms with a mask of the remaining photoresist pattern to form trenches 4. Then, the photoresist and etching reaction products are stripped by oxygen ashing and a treatment with persulfuric acid and a dilute fluoric acid aqueous solution to form a structure as shown in FIG. 7(a).
Then, thermal oxide films 5 are formed on the trench surfaces to a thickness of about 300 Angstroms, and then a CVD oxide film 6 is buried by a biased high density plasma (HDP) CVD process to form a structure as shown in FIG. 7(b).
Then, the CVD oxide film 6 is polished by a chemical mechanical polished (CMP) process to form a structure as shown in FIG. 7(c).
Then, the Si3N4 film patterns 3-1 and 3-2 are stripped by a thermal phosphoric acid process to provide a shallow trench isolation (STI) structure as shown in FIG. 7(d).
In the above CMP process, the Si3N4 film 3 is used as a polish stopper film. The polished amounts are different between the dense pattern 3-1 and coarse pattern 3-2 of the Si3N4 stopper film as shown in FIG. 7(c). The device characteristics (transistor hump characteristics) make it necessary that the height of the isolation oxide film 6-2 from the silicon surface be no less than 0 Angstrom even in the coarse pattern region where the CMP amount is large. Consequently, the height of the isolation oxide film 6-1 from the silicon surface in the dense pattern area becomes no less than about 1000 Angstroms. Where there is such a stepwise difference in polished amount between the isolation areas, it is necessary to strip by over-etching the stringer of a gate conductive pattern which crosses these isolation areas, thus presenting a problem that the margin of a remaining gate oxide film becomes too small.
Accordingly, it is an object of the invention to provide a method of making a semiconductor device using an STI process, wherein there are few variations in height of the isolation oxide film from the silicon surface.
It is another object of the invention to provide a method of making a semiconductor device, wherein the pad oxide film can be removed simultaneously.
It is still another object of the invention to provide a method of making a semiconductor device, which has an improved spin-on-glass (SOG) removal margin.
It is yet another object of the invention to provide a method of making a semiconductor device, which has a reduced manufacturing cost.
It is another object of the invention to provide a method of making a semiconductor device, wherein the thermal phosphoric acid process can be removed.
It is still another object of the invention to provide a method of making a semiconductor device, wherein detecting a finishing point of etching is made easy.
According to an aspect of the invention, there is provided a method of making a semiconductor device which comprises the steps of depositing a Si3N4 film by a chemical vapor deposition (CVD) process, polishing a CVD oxide film by a chemical mechanical polishing (CMP), planarizing with a coat of organic spin-on-glass (SOG) a rough surface of the silicon substrate resulting from a pattern dependency of polished amounts in the CMP process and etching back evenly the organic SOG and the CVD oxide film buried in the trench at an etching selectivity ratio of 1.
According to an another aspect of the invention, there is provided a method of making a semiconductor device which comprises the steps of depositing a Si3N4 film by CVD process, polishing a CVD oxide film by CMP, planarizing with a coat of organic SOG a rough surface of the silicon substrate resulting from a pattern dependency of polished amounts in the CMP process and etching back evenly the organic SOG and the CVD oxide film buried in the trench at an etching selectivity ratio less than 1.
According to still another aspect of the invention, there is provided a method of making a semiconductor device which comprises the steps of depositing a Si3N4 film by CVD process, polishing a CVD oxide film by CMP, planarizing with a coat of organic SOG a rough surface of said silicon substrate resulting from a pattern dependency of polished amounts in the CMP process and etching back evenly the organic SOG and the CVD oxide film buried in the trench by a two-step etching under two conditions that selectivity ratios are 1 and less than 1, respectively.
According to yet another aspect of the invention, there is provided a method of making a semiconductor device which comprises the steps of depositing a Si3N4 film by CVD process, planarizing with a coat of organic SOG a rough surface of the silicon substrate, and etching back evenly the organic SOG and the CVD oxide film buried in the trench at an etching selectivity ratio of 1, wherein no CMP is included in steps of the aspect.
According to another aspect of the invention, there is provided a method of making a semiconductor device which comprises the steps of depositing a poly-silicon film by CVD process, planarizing with a coat of organic SOG a rough surface of the silicon substrate, and etching back evenly the organic SOG and the CVD oxide film buried in the trench at an etching selectivity ratio of 1 and etching the CVD oxide film with a fluoric acid aqueous solution, wherein no CMP is used.
According to still another aspect of the invention, there is provided a method of making a semiconductor device which comprises the steps of depositing a O3-TEOS-NGS film by CVD process, planarizing with a coat of organic SOG a rough surface of the silicon substrate, etching back evenly the organic SOG and the CVD oxide film buried in the trench at an etching selectivity ratio of 1 and etching the CVD oxide film and the O3-TEOS-NGS film with a fluoric acid aqueous solution, wherein no CMP is used.